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July 2003 Advance Information
PulseC re AS80SSTVF16857
DDR 14-Bit Registered Buffer
Features
* * * * * * * Differential clock signals Meets SSTL_2 class II specifications on outputs Supports SSTL_2 Class I and II specifications Low voltage operation - VDD = 2.3V to 2.7V Available in 48-pin TSSOP and TVSOP package Operates at 2.3V to 2.7V for PC1600, PC2100, and PC2700; 2.5V to 2.7V for PC3200 Pinout and Functionality Compatible with JEDEC Standard SSTV16857
Recommended Applications
* * * DDR memory modules Provides complete DDR DIMM logic solution with PCV857 SSTL_2-compatible data registers
Block Diagram
Pin Configuration
CLK CLKB RESETB D1 VREF
38 39 34 48 35
R CLK D1
Q1
To 13 other channels
Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
D1 D2 GND VDD D3 D4 D5 D6 D7 CLKB CLK VDD GND VREF RESETB D8 D9 D10 D11 D12 VDD GND D13 D14
48-Pin TSSOP & TVSOP 6.10 mm body, 0.50 mm pitch = TSSOP 4.40 mm body, 0.40 mm pitch = TSSOP (TVSOP)
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AS80SSTVF16857
Truth Table1
Inputs RESETB L H H H CLK X or floating L or H CLKB X or floating L or H D X or floating H L X Q outputs Q L H L Q 02
1 H = high signal level, L = low signal level, = transition low to high, = transition high to low, X = don't care. 2 Output level before the indicated steady state input conditions were established.
Description
The 14-bit PC16857 is a universal bus driver designed for 2.3 V to 2.7 V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESETB input. Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The positive edge of CLK is used to trigger the data flow, and CLKB is used to maintain sufficient noise margins, whereas RESETB, an LVCMOS asynchronous signal, is intended for use only at power-up. PC16857 supports low-power standby operation. A logic level low at RESETB assures that all internal registers and outputs (Q) are reset to the logic low state, and that all input receivers, data (D), and clock (CLK/CLKB) are switched off. Note that RESETB must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up. In the DDR DIMM application, RESETB is specified to be completely asynchronous with respect to CLK and CLKB, therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic low level quickly relative to the time to disable the differential input receivers. This ensures there are no glitches on the output. When coming out of low power standby state, however, the register will become active quickly relative to the time to enable the differential input receivers. When the data inputs are at a logic level low and the clock is stable during the low-tohigh transition of RESETB until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic low level.
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Pin Configuration
Pin number 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 3, 8, 13, 22, 27, 36, 46 4, 9, 12, 16, 21 25, 26, 29, 30, 31, 32, 33, 40, 41, 42, 43, 44, 47,48 38 39 28, 37, 45 34 35 Pin name Q(14:1) GND VDDQ D(14:1) CLK CLKB VDD RESETB VREF Type Output PWR PWR Input Input Input PWR Input Input Description Data output Ground Output supply voltage Data input Positive clock input Negative clock input Core supply voltage Reset (active low) Input reference voltage
Absolute Maximum Ratings
Storage temperature Supply voltage Input voltage
1 1,2
- 65 C to +150 C -0.5 to 3.6 V -0.5 to VDD + 0.5 -0.5 to VDDQ + 0.5 50 mA 50 mA 50 mA 100 mA 55 C/W
3
Output voltage
Input clamp current Output clamp current Continuous output current VDD, VDDQ, or GND current/pin Package thermal impedance
1 The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2 This current will flow only when the output is in the high state level V0 > VDDQ. 3 The package thermal impedance is calculated in accordance with JESD 51.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only, and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
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Recommended Operating Conditions
Guaranteed by design. Not 100% tested in production. Parameter VDD VDDQ Supply voltage Output supply voltage PC1600, PC2100, PC2700 PC3200 VREF VTT VI VIH(DC) VIH(AC) VIL(DC) VIL(AC) VIH VIL VICR VID VIX IOH IOL TA Reference voltage (VREF=VDDQ/2) Termination voltage Input voltage DC input high voltage AC input high voltage DC input low voltage AC input low voltage Input high voltage level Input low voltage level Common mode input range Differential input voltage High-level output current Low-level output current Operating free-air temperature 0 RESETB CLK,CLKB 1.7 0.7 0.97 0.36 (VDDQ/2) - 0.2 (VDDQ/2) + 0.2 -20 20 70 1.53 Data inputs PC1600, PC2100, PC2700 PC3200 Description Min VDDQ 2.3 2.5 1.15 1.25 VREF - 0.04 0 VREF + 0.15 VREF + 0.31 VREF - 0.15 VREF - 0.31 1.25 1.3 VREF Typ Max 2.7 2.7 2.7 1.35 1.35 VREF + 0.04 VDD Units V V V V V V V V V V V V V V V V mA mA C
Cross-point voltage of differential clock pair
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DC Electrical Characteristics for PC1600, PC2100, and PC2700
TA = 0 C to 70 C, VDD = 2.5 0.2 V, and VDDQ = 2.5 0.2 V (unless otherwise stated) Guaranteed by design. Not 100% tested in production. Symbol VIK VOH Parameters Test conditions II = -18 mA IOH = -100 A IOH = -16 mA VOL II IDD All inputs Standby (static) Operating (static) Dynamic operating (clock only) IOL = 100 A IOL = 16 mA VI = VDD or GND RESETB = GND VI = VIH(AC) or VIL(AC), RESETB = VDD RESETB = VDD, VI = VIH(AC) or VIL(AC), CLK and CLKB = switching 50% duty cycle RESETB = VDD, VI = VIH(AC) or VIL(AC), CLK and CLKB switching 50% duty cycle One data input switching at half clock frequency, 50% duty cycle IOH = -20 mA IOL = 20 mA IO = 20 mA, TA = 25 C VI = VREF 310 mV, VICR = 1.25 V, CI CLK and CLKB RESETB VI(PP) = 360 mV VI=VDD or GND 2.5 V 2.5V 2.5 2.5 3.5 3.5 pF pF 2.3 V to 2.7 V 2.3 V to 2.7 V 2.5 V 2.5 V 2.5 7 7 13.5 13 20 20 4 3.5 VDD 2.3 V 2.3 V to 2.7 V 2.3 V 2.3 V to 2.7 V 2.3 V 2.7 V 2.7 V 2.7 V VDD 0.2 1.95 0.2 0.35 5 0.01 25 Min Typ Max -1.2 Units V V V V V A A mA A/ clock MHz / clock MHz/ data input pF
2.7 V IO = 0
28
IDDD Dynamic operating (per each data input)
2.7 V
15
rOH rOL rO(D)
Output high Output low |rOH - rOL| each separate bit Data inputs
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DC Electrical Characteristics for PC3200
TA = 0 C to 70 C, VDD = 2.6 0.1 V, and VDDQ = 2.6 0.1 V (unless otherwise stated) Guaranteed by design. Not 100% tested in production. Symbol VIK VOH Parameters Test conditions II = -18 mA IOH = -100 A IOH = -16 mA VOL II IDD All inputs Standby (static) Operating (static) Dynamic operating (clock only) IOL = 100 A IOL = 16 mA VI = VDD or GND RESETB = GND VI = VIH(AC) or VIL(AC), RESETB = VDD RESETB = VDD, VI = VIH(AC) or VIL(AC), CLK and CLKB = switching 50% duty cycle RESETB = VDD, VI = VIH(AC) or VIL(AC), CLK and CLKB switching 50% duty cycle One data input switching at half clock frequency, 50% duty cycle IOH = -20 mA IOL = 20 mA IO = 20 mA, TA = 25 C VI = VREF 310 mV, VICR = 1.25 V, Ci CLK and CLKB RESETB VI(PP) = 360 mV VI=VDD or GND 2.6 V 2.6V 2.5 2.5 3.5 3.5 pF pF 2.5 V to 2.7 V 2.5 V to 2.7 V 2.6 V 2.6 V 2.5 7 7 13.5 13 20 20 4 3.5 VDD 2.5 V 2.5 V to 2.7 V 2.5 V 2.5 V to 2.7 V 2.5 V 2.7 V 2.7 V 2.7 V VDD 0.2 1.95 0.2 0.35 5 0.01 25 Min Typ Max -1.2 Units V V V V V A A mA A/ clock MHz / clock MHz/ data input pF
2.7 V IO = 0
28
IDDD Dynamic operating (per each data input)
2.7 V
15
rOH rOL rO(D)
Output high Output low |rOH - rOL| each separate bit Data inputs
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Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted.) Guaranteed by design. Not 100% tested in production.
VDD = 2.5 V 0.2 V VDD = 2.6 V 0.1 V
Units MHz ns ns ns ns ns ns ns
Symbol fclock tw tact tinact tSu th tSL Clock frequency
Parameters Pulse duration, CLK, CLKB high or low Differential inputs inactive Setup time, fast slew rate Setup time, slow slew Hold time, fast slew rate time1
2
Min 2.5
Max 200
Min 2.5
Max 280 22 22
22 22 Data before CLK, CLKB Data after CLK, CLKB 0.75 0.9 0.75 0.9 1 4 0.4 0.5 0.4 0.5 1
Differential inputs inactive time
3,5
rate4,5
3,5 4,5
Hold time, slow slew rate
Output slew rate, measurement point at 20% and 80%
4
V/ns
1 Data inputes must be low a minimum time of tact max, after RESETB is taken high. 2 Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESETB is taken low. 3 For data signal input slew rate > 1V/ns. 4 For data signal input slew rate > 0.5 V/ns and < 1 V/ns. 5 CLK, CLKB signals input slew rates are > 1 V/ns.
Switching Characteristics for PC1600, PC2100, and PC2700
(Over recommended operating free-air temperature range unless otherwise noted) (See test circuits and switching waveforms) VDD = 2.5 V 0.2 V Symbol fmax tpd tphl CLK, CLKB RESETB Q Q From (input) To (output) Min 200 1.1 2.8 5.0 Typ Max Units MHz ns ns
Switching Characteristics for PC3200
(Over recommended operating free-air temperature range unless otherwise noted) (See test circuits and switching waveforms) VDD = 2.6 V 0.1 V Symbol fmax tpd tphl CLK, CLKB RESETB Q Q From (input) To (output) Min 280 1.1 2.2 5.0 Typ Max Units MHz ns ns
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Parameter Measurement Information:
VDD = 2.5 V 0.2 V for PC1600, PC2100,& PC2700 and VDD= 2.6 V 0.1V for PC3200
VTT RL = 50 From output under test Test point CL = 30 pF1 Load circuit
1
CL includes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50 , input slew rate = 1 V/ns 20% (unless otherwise specified). The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ/2. VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. VIL = VREF - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. tPLH and tPHL are the same as tpd. Input active and inactive times
LVCMOS RESETB VDD/2 tinact 10%
1
Input
IDD1
VDD/2 tact 90%
VDD 0V IDDH IDDL
IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Pulse duration tw Input VREF VREF VIH VIL
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Setup and hold times VI(pp) Timing input ts Input Propagation delay times VI(pp) Timing input VICR tPLH VTT VICR tPHL VTT VOH VOL VREF VICR th VREF VIH VIL
Output
LVCMOS RESETB Input VDD/2 tPHL Output VTT
VIH VIL
VOH VOL
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Package Dimensions (48- Pin TSSOP)
Millimeters N c L Symbol A A1 E1 Index area 12 D A2 e b A1 A
Seating plane
Inches Min - 0.002 0.32 0,007 0.0035 Max 0.047 0.006 0.041 0.011 0.008
Min - 0.05 0.80 0.17 0.09
Max 1.20 0.15 1.05 0.27 0.20
E
A2 b c D E E1 e L N a aaa C
See variations below 8.10 basic 6.00 0.45 0 - 6.20 0.75 8 0.10 0.50 basic 0.319 basic 0.236 0.018 0 - 0.244 0.030 8 0.004 0.020 basic
See variations below
6.10 mm (240 mil) body, 0.50 mm (0.020 mil) pitch TSSOP
aaa Variations:
D (mm) N 48 Min 12.40 Max 12.60
D (inch) Min 0.488 Max 0.496
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Package Dimensions (Alternate Size)
Millimeters N c L Symbol A A1 E1 Index area 12 D A2 e b A1 A
Seating plane
Inches Min - 0.002 0.32 0,005 0.0035 Max 0.047 0.006 0.041 0.009 0.008
Min - 0.05 0.80 0.13 0.09
Max 1.20 0.15 1.05 0.23 0.20
E
A2 b c D E E1 e L N a aaa C
See variations below 6.40 basic 4.30 0.45 0 - 4.50 0.75 8 0.08 0.40 basic 0.252 basic 0.169 0.018 0 - 0.177 0.030 8 0.003 0.016 basic
See variations below
4.40 mm (173 mil) body, 0.40 mm (16 mil) pitch TVSOP
aaa Variations:
D (mm) N 48 Min 9.60 Max 9.80
D (inch) Min 0.378 Max 0.386
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Ordering Information
Quantity per reel 2500 2500
Ordering Number AS80SSTVF16857-48TT AS80SSTVF16857-48TR AS80SSTVF16857-48VT AS80SSTVF16857-48VR
Marking
Package Type
Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
AS80SSTVF16857T 48-pin TSSOP, tube AS80SSTVF16857T 48-pin TSSOP, tape and reel AS80SSTVF16857V 48-pin TVSOP, tube AS80SSTVF16857V 48-pin TVSOP, tape and reel
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